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www.annauniv.edu/ BE ECE 6TH SEMESTER QUESTION BANK VLSI DESIGN

QUESTION BANK




SUBJECT CODE : EC 2354

SUBJECT NAME : VLSI DESIGN




PART - A ( 2 marks)

1. What are the different MOS layers?

2. What are the two types of layout design rules?

3. Define rise time and fall time.

4. What is a pull down device?

5. What is mean by “Epitaxy”?

6. What is isolation?

7. What are the steps involved in manufacturing of IC?

8. What is the special feature of Twin-Tub process?

9. Draw the Isotropic etching process diagram.

10. What is silicide?

11. What is AOI?

12. Define fabrication process.

13. Draw the graph of n-MOS depletion mode.

14. Draw the Dc transfer characteristics curve.

11. Define noise margin.

15. Draw the symbol for tristate inverter.

16. Differentiate the nMOS from pMOS.

17. What are all the factors can be extracted from the Vth equation.

18. Define the Power dissipation

19. Define bit and byte.

20 Define FSM.

21 What do you mean by Data flow model?

22. Define Mealy network.

23. What is component in VHDL?

24 Which MOS can pass logic 1 and logic 0 strongly?

25 What is AOI logic function.

26 What are the methods for programming the PALs?

27 What are all the types of programming PALs?

28 Define PLD.

29 Draw the basic PLA.

30 Differentiate the PLA from the PAL.

31. Define test bench.

32. What is FPGA?

33. What is super buffer?

34. What is meant by Steering logic?

35. Give the advantages and disadvantages of SOI.




PART-B (16&8 Marks)




1. Differentiate the p-well CMOS process from n-well CMOS process. Explain the n-well CMOS process to fabricate the n-switches.

2. Discuss the steps involved in IC fabrication process.

3. Describe n-well process in detail.

4. Explain the DC characteristics of CMOS inverter with neat sketch.

5. Explain channel length modulation and body effect.

6. Explain the different regions of operation in a MOS transistor.

7. Write a note on MOS models.

8. Explain in detail any five operators used in VHDL.

9. Write the VHDL code for 4 bit ripple carry full adder.

10. Give the structural description for priority encoder using VHDL.

11 List out the layout design rule. And draw the physical layout for one basic gate and two universal gates.

12 Explain the n MOS and p MOS enhancement transistor with its physical structure.

13. Derive and explain the

(I) Threshold voltage equation,

(II) MOS DC equation.

14. Explain the complimentary CMOS inverter DC characteristics.

15. Write short notes on

(I) Noise Margin,

(II) Rise Time,

(III) Fall Time.

16. Develop the project using VHDL to realize the function of a ripple carry adder and draw its RTL.

17. Design a full adder by cascading two half adders and develop a project to realize it in model simulator 6.0.

18 Briefly explain the following terms

(i) Design of switches with MOSFETs,

(ii) Transmission gate,

(iii) Muxs using TG.

19. Draw the physical layout for the following Boolean expression

a. y = (a +b)’ + c + de

b. x = (lmnop)’ + q’(r’s + rs’)

20. Differenced the PALs from PLAs. And explain the 22V10 standard logic structure with the architecture.

21. Explain the methods used to programme the PALs with neat diagram.

22. Explain the Field programmable gate array with the architecture and logic blocks.

23. Draw and explain the typical architecture of PAL.

24. Explain test bench with an example and ways of generating waveforms.

25. Write a VHDL description to design Flip Flops( RS, JK, D, T) and write its test bench.

26. Write a VHDL description to design 8:1 MUX using two 4:1 MUX.

27. Write a VHDL description to design 8:1 MUX and DEMUX.

28. Write a VHDL description to design a undown counter and write its test bench.

29. Explain type,Operators, timing controls, Procedural assignments.

30 Draw and explain with diagrams tally circuits.

31. Draw and explain barrel shifters.

32. Explain with neat diagrams dynamic CMOS clocking.

33. Derive an expression for pull up and pull down ratio for transistors.

34. Describe in detail the chip with programmable logic structures.

35. Explain packages in vhdl with example.

36. With neat diagram explain finite state machine PLA.

37. Expain structured design of combinational circuits- EXOR Structure, Multiplex Structure.

39. Discuss the steps involved in fabrication of BICMOS technology.






















3 comments:

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